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RT8055B 1 ds8055b-03 april 2011 www.richtek.com features z z z z z high efficiency : up to 95% z z z z z low r ds(on) internal switches : 100m z z z z z programmable frequency : 300khz to 2mhz z z z z z no schottky diode required z z z z z 0.8v reference voltage allows for low output voltage z z z z z forced continuous mode operation z z z z z 100% duty cycle operation z z z z z input over voltage protection z z z z z power good output voltage indicutor z z z z z rohs compliant and halogen free general description the RT8055B is a high efficiency synchronous, step-down dc/dc converter. its input voltage range is from 2.6v to 5.5v and provides an adjustable regulated output voltage from 0.8v to 5v while delivering up to 3a of output current. the internal synchronous low on-resistance power switches increase efficiency and eliminate the need for an external schottky diode. the switching frequency is set by an external resistor. the 100% duty cycle provides low dropout operation extending battery life in portable systems. current mode operation with external compensation allows the transient response to be optimized over a wide range of loads and output capacitors. the RT8055B is operated in forced continuous pwm mode which minimizes ripple voltage and reduces the noise and rf interference. the RT8055B is available in the wdfn-10l 3x3 package. ordering information pin configurations (top view) wdfn-10l 3x3 3a, 2mhz, synchronous step-down converter note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. applications z portable instruments z battery-powered equipment z notebook computers z distributed power systems z ip phones z digital cameras z 3g/3.5g data card shdn/rt gnd pgnd lx comp fb pgood pvdd vdd lx 9 8 7 1 2 3 4 5 10 6 gnd 11 marking information k3= : product code ymdnn : date code k3=ym dnn RT8055B package type qw : wdfn-10l 3x3 (w-type) lead plating system g : green (halogen free and pb free)
RT8055B 2 ds8055b-03 april 2011 www.richtek.com functional pin description pin no. pin name pin function 1 shdn/rt shutdown control or frequency setting input. connect a resistor to ground from this pin sets the switching frequency. force this pin to v dd or gnd causes the device to be shut down. 2, 11 (exposed pad) gnd signal ground. all small-signal components and compensation components should be connected to this ground, which in turn connects to pgnd at one point. the exposed pad must be soldered to a large pcb and connected to gnd for maximum power dissipation. 3, 4 lx internal power mosfet switches output. connect this pin to the inductor. 5 pgnd power ground. connect this pin close to the negative terminal of c in and c out . 6 pvdd power supply input. decouple this pin to pgnd with a capacitor. 7 vdd signal supply input. decouple this pin to gnd with a capacitor. generally, v dd is equal to pvdd. 8 pgood power good indicator. the pin is an open drain logic output that is pulled to ground. 9 fb feedback pin. this pin receives the feedback voltage from a resistive divider connected across the output. 10 comp error amplifier compensation point. the current comparator threshold increases with this control voltage. connect external compensation elements to this pin to stabilize the control loop. typical application circuit note : using x5r/x7r ceramic capacitors table 1. recommended component selsction v out r1 (k ) r2 (k ) r comp (k ) c comp (nf) l1 ( h) c ou t ( f) 3.3 75 24 30 0.47 2.2 22 x 2 2.5 51 24 27 0.47 2.2 22 x 2 1.8 30 24 22 0.47 2.2 22 x 2 1.5 21 24 18 0.47 2.2 22 x 2 1.2 12 24 15 0.47 1.0 22 x 2 1.0 6 24 13 0.47 1.0 22 x 2 22f x 2 pvdd lx shdn/rt RT8055B vdd comp 2h v out1 l1 10 3, 4 c out gnd fb pgnd 9 r1 r2 75k 24k 3.3v/3a r comp 30k c comp 470pf 22pf c f r3 c1 r4 100k 6 7 pgood c in 22f v in 5v pgood 8 1 r osc 180k 2,11 (exposed pad) 5
RT8055B 3 ds8055b-03 april 2011 www.richtek.com function block diagram driver control logic 0.9v oc limit isen slope comp. osc output clamp ea 0.8v internal soft-star por gnd fb pvdd vdd pgnd lx otp vref sd nisen n-mosfet i lim 0.7v 0.4v shdn/rt comp pgood
RT8055B 4 ds8055b-03 april 2011 www.richtek.com absolute maximum ratings (note 1) z supply input voltage, vdd, pv dd ---------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin switch voltage -------------------------------------------------------------------------------------------- ? 0.3v to (pvdd + 0.3v) <30ns ---------------------------------------------------------------------------------------------------------------- ? 5v to 7.5v z other i/o pin v oltages ------------------------------------------------------------------------------------------- ? 0.3v to 6.5v z lx pin switch current -------------------------------------------------------------------------------------------- 4a z power dissipation, p d @ t a = 25 c wdfn-10l 3x3 ----------------------------------------------------------------------------------------------------- 1.667w z package thermal resistance (note 2) wdfn-10l 3x3, ja ----------------------------------------------------------------------------------------------- 60 c/w wdfn-10l 3x3, jc ----------------------------------------------------------------------------------------------- 7.8 c/w z junction temperature --------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------ ----------------------------------------------------- 260 c z storage temperature range ------------------------------------------------------------------------------------ ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) -------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ---------------------------------------------------------------------------------------------- 200v electrical characteristics (v dd = 3.3v, t a = 25 c, unless otherwise specified) to be continued recommended operating conditions (note 4) z supply input voltage ---------------------------------------------------------------------------------------------- 2.6v to 5.5v z junction temperature range ------------------------------------------------------------------------------------ ? 40 c to 125 c z ambient temperature range ------------------------------------------------------------------------------------ ? 40 c to 85 c parameter symbol test conditions min typ max unit input voltage range v dd 2.6 -- 5.5 v feedback reference voltage v ref 0.784 0.8 0.816 v feedback leakage current i fb v fb = 3.3v -- -- 0.1 a active, v fb = 0.7v, not switching -- 500 -- a dc bias current shutdown -- -- 1 a output voltage line regulation v line v in = 2.6v to 5.5v -- 0.1 -- %/v output voltage load regulation v load v in = 5v, v out = 3.3v, i out = 0a to 3a -- 0.4 -- % error amplifier transconductance gm -- 400 -- a/v current sense transresistance r s -- 0.4 -- rt leakage current shdn/rt = v in = 5.5v -- -- 1 a r osc = 180k 1.44 1.8 2.16 mhz switching frequency adjustable switching frequency range 0.3 -- 2 mhz switch on resistance, high r ds(on)_p i sw = 0.3a -- 100 160 m switch on resistance, low r ds(on)_n i sw = 0.3a -- 100 170 m
RT8055B 5 ds8055b-03 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in the natural convection at t a = 25 c on a high effective thermal conductivity four layers test board of jedec 51-7 thermal measurement standard. the case point of jc is on the exposed pad for the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit peak current limit i lim 3.5 -- -- a v dd rising -- 2.4 -- v under voltage lockout threshold v dd falling -- 2.2 -- v shutdown threshold v shd n v shd n rising -- v in ? 0.85 v in ? 0.4 v power good (pgood) v out falling (fault) -- 87 -- %v ou t v out rising (good) -- 90 -- %v ou t v out rising (fault) -- 114 -- %v ou t power good threshold v out falling (good) -- 111 -- %v ou t
RT8055B 6 ds8055b-03 april 2011 www.richtek.com typical operating characteristics output voltage vs. input voltage 3.30 3.31 3.32 3.33 3.34 3.35 3.36 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) output voltage (v) i out = 0a, v out = 3.3v efficiency vs. output current 0 10 20 30 40 50 60 70 80 90 100 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output current (a) efficiency (%) v in = 5v, v out = 3.3v switching frequency vs. temperature 1.5 1.6 1.7 1.8 1.9 2.0 2.1 -50 -25 0 25 50 75 100 125 temperature (c) switching frequency (mhz) 1 v in = 5v, v out = 3.3v i out = 0.3a, f sw = 1.8mhz v in uvlo vs. temperature 2.00 2.05 2.10 2.15 2.20 2.25 2.30 2.35 2.40 2.45 2.50 -50 -25 0 25 50 75 100 125 temperature (c) v in uvlo (v) rising falling v out = 3.3v output voltage vs. output current 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 output current (a) output voltage (v) v in = 5v, v out = 3.3v switching frequency vs. input voltage 1.5 1.6 1.7 1.8 1.9 2.0 2.1 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) switching frequency (mhz) 1 v in = 5v, v out = 3.3v i out = 0.3a, f sw = 1.8mhz
RT8055B 7 ds8055b-03 april 2011 www.richtek.com output ripple time (500ns/div) v in = 5v, v out = 3.3v i out = 3a v lx (5v/div) v out (5mv/div) reference voltage vs. temperature 0.760 0.768 0.776 0.784 0.792 0.800 0.808 0.816 0.824 0.832 0.840 -50 -25 0 25 50 75 100 125 temperature (c) reference voltage (v) output current limit vs. temperature 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 -50 -25 0 25 50 75 100 125 temperature (c) output current limit (a ) v in = 5v, v out = 3.3v output ripple time (500ns/div) v in = 5v, v out = 3.3v i out = 0a v lx (5v/div) v out (5mv/div) output voltage vs. temperature 3.20 3.22 3.24 3.26 3.28 3.30 3.32 3.34 3.36 3.38 3.40 -50 -25 0 25 50 75 100 125 temperature (c) output voltage (v) v in = 5v, v out = 3.3v i out = 0a output current limit vs. input voltage 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 input voltage (v) output current limit (a) v out = 3.3v
RT8055B 8 ds8055b-03 april 2011 www.richtek.com load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 3.3v i out = 0a to 2a load transient response time (100 s/div) i out (1a/div) v out (200mv/div) v in = 5v, v out = 3.3v i out = 0a to 3a power on from v in time (1ms/div) v in = 5v, v out = 3.3v v in (2v/div) pgood (2v/div) v out (2v/div)
RT8055B 9 ds8055b-03 april 2011 www.richtek.com application information the basic RT8055B application circuit is shown in typical application circuit. external component selection is determined by the maximum load current and begins with the selection of the inductor value and operating frequency followed by c in and c out . output voltage setting the output voltage is set by an external resistive divider according to the following equation : where v ref equals to 0.8v typical. the resistive divider allows the fb pin to sense a fraction of the output voltage as shown in figure 1. figure 1. setting the output voltage ? ? ? ? ? ? + = r2 r1 1 v v ref out soft-start the RT8055B contains an internal soft-start clamp that gradually raises the clamp on the comp pin. power good output the power good output is an open drain output and requires a pull up resister. when the output voltage is 14% above or 13% below its set voltage, pgood will be pulled low. it is held low until the output voltage returns to within the allowed tolerances once more. in soft-start, pgood is actively held low and is allowed to transition high until the soft-start is finished and the output voltage reaches 90% of its set voltage. operating frequency selection of the operating frequency is a tradeoff between efficiency and component size. high frequency operation allows the use of smaller inductor and capacitor values. operation at lower frequency improves efficiency by reducing internal gate charge and switching losses but requires larger inductance and/or capacitance to maintain low output ripple voltage. figure 2 100% duty cycle operation when the input supply voltage decreases toward the output voltage, the duty cycle increases toward the maximum on-time. further reduction of the supply voltage forces the main switch to remain on for more than one cycle eventually reaching 100% duty cycle. the output voltage will then be determined by the input voltage minus the voltage drop across the internal p-mosfet and the inductor. low supply operation the RT8055B is designed to operate down to an input supply voltage of 2.6v. one important consideration at low input supply voltages is that the r ds(on) of the p- channel and n-channel power switches increases. the user should calculate the power dissipation when the RT8055B is used at 100% duty cycle with low input voltages to ensure that thermal limits are not exceeded. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 200 400 600 800 1000 r osc (k ) switching frequency (mhz) 1 r osc (k ) r rt = 180k for 1.8mhz the operating frequency of the RT8055B is determined by an external resistor that is connected between the shdn/rt pin and gnd. the value of the resistor sets the ramp current that is used to charge and discharge an internal timing capacitor within the oscillator. the rt resistor value can be determined by examining the frequency vs. r rt curve. although frequencies as high as 2mhz are possible, the minimum on-time of the RT8055B imposes a minimum limit on the operating duty cycle. the minimum on-time is typically 110ns. therefore, the minimum duty cycle is equal to 100 x 110ns x f (hz). RT8055B fb gnd v out r1 r2
RT8055B 10 ds8055b-03 april 2011 www.richtek.com this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. choose a capacitor rated at a higher temperature than required. several capacitors may also be paralleled to meet size or height requirements in the design. the selection of c out is determined by the effective series resistance (esr) that is required to minimize voltage ripple and load step transients, as well as the amount of bulk capacitance that is necessary to ensure that the control loop is stable. loop stability can be checked by viewing the load transient response as described in a later section. the output ripple, v out , is determined by : ? ? ? ? ? ? + out l out 8fc 1 esr i v slope compensation and inductor peak current slope compensation provides stability in constant frequency architectures by preventing sub-harmonic oscillations at duty cycles greater than 50%. it is accomplished internally by adding a compensating ramp to the inductor current signal. normally, the maximum inductor peak current is reduced when slope compensation is added. in the RT8055B, however, separated inductor current signals are used to monitor over current condition. this keeps the maximum output current relatively constant regardless of duty cycle. short circuit protection when the output is shorted to ground, the inductor current decays very slowly during a single switching cycle. a current runaway detector is used to monitor inductor current. as current increasing beyond the control of current loop, switching cycles will be skipped to prevent current runaway from occurring. inductor selection the inductor value and operating frequency determine the ripple current according to a specific input and output voltage. the ripple current i l increases with higher v in and decreases with higher inductance. out out l in vv i = 1 fl v ??? ? ?? ??? ? ??? ? out out l(max) in(max) vv l = 1 fi v ??? ? ? ??? ? ??? ? having a lower ripple current reduces not only the esr losses in the output capacitors but also the output voltage ripple. however, it requires a large inductor to achieve this goal. for the ripple current selection, the val ue of i l = 0.4(i max ) will be a reasonable starting point. the large st ripple current occurs at the highest v in . to guarantee that the ripple current stays below the specified maximum, the inductor value should be chosen according to the following equation : the inductor's current rating (caused a 40 c temperature rising from 25 c ambient) should be greater than the maximum load current and its saturation current should be greater than the short circuit peak current limit. the output ripple is highest at maximum input voltage since i l increases with input voltage. multiple capacitors placed in parallel may be needed to meet the esr and rms current handling requirements. dry tantalum, special polymer, aluminum electrolytic and ceramic capacitors are all available in surface mount packages. special polymer capacitors offer very low esr but have lower capacitance density than other types. tantalum capacitors have the highest capacitance density but it is important to only use types that have been surge tested for use in switching power supplies. aluminum electrolytic capacitors have significantly higher esr but can be used in cost-sensitive applications provided that consideration is given to ripple current ratings and long term reliability. ceramic capacitors have excellent low esr characteristics but can have a high voltage coefficient and audible piezoelectric effects. the high q of ceramic capacitors with trace inductance can also lead to significant ringing. c in and c out selection the input capacitance, c in , is needed to filter the trapezoidal current at the source of the top mosfet. to prevent large ripple voltage, a low esr input capacitor sized for the maximum rms current should be used. rms current is given by : out in rms out(max) in out v v ii 1 vv =?
RT8055B 11 ds8055b-03 april 2011 www.richtek.com using ceramic input and output capacitors higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. their high ripple current, high voltage rating and low esr make them ideal for switching regulator applications. however, care must be taken when these capacitors are used at the input and output. when a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, v dd . at best, this ringing can couple to the output and be mistaken as loop instability. at worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at v in large enough to damage the part. thermal considerations for continuous operation, do not exceed absolute maximum operation junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, the rate of surroundings airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum operation junction temperature, t a is the ambient temperature and the ja is the junction to ambient thermal resistance. for recommended operating conditions specification of RT8055B, the maximum junction temperature is 125 c and t a is the maximum ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wdfn-10l 3x3 packages, the thermal resistance ja is 60 c/w on the standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by following formula : p d(max) = (125 c ? 25 c) / (60 c/w) = 1.667w for wdfn-10l 3x3 package the maximum power dissipation depends on operating ambient temperature for fixed t j(max) and thermal resistance ja . for RT8055B package, the figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. figure 3. derating curves for RT8055B package layout considerations follow the pcb layout guidelines for optimal performance of RT8055B. ` a ground plane is recommended. if a ground plane layer is not used, the signal and power grounds should be segregated with all small-signal components returning to the gnd pin at one point that is then connected to the pgnd pin close to the ic. the exposed pad should be connected to gnd. ` connect the terminal of the input capacitor(s), c in , as close as possible to the pvdd pin. this capacitor provides the ac current into the internal power mosfets. ` lx node is with high frequency voltage swing and should be kept within small area. keep all sensitive small-signal nodes away from the lx node to prevent stray capacitive noise pick-up. ` flood all unused areas on all layers with copper. flooding with copper will reduce the temperature rise of powercomponents. you can connect the copper areas to any dc net (pvdd, vdd, vout, pgnd, gnd, or any other dc rail in your system). ` connect the fb pin directly to the feedback resistors. the resistor divider must be connected between v out and gnd. 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0255075100125 ambient temperature (c) maximum power dissipation (w ) four layers pcb
RT8055B 12 ds8055b-03 april 2011 www.richtek.com component supplier series inductance ( h) dcr (m ) current rating (ma) dimensions (mm) taiyo yuden nr 8040 2 9 7800 8x8x4 table 2. inductors component supplier part no. capacitance ( f) case size tdk c3225x5r0j226m 22 1210 tdk c2012x5r0j106m 10 0805 panasonic ecj4yb0j226m 22 1210 panasonic ecj4yb1a106m 10 1210 taiyo yuden lmk325bj226ml 22 1210 taiyo yuden jmk316bj226ml 22 1206 taiyo yuden jmk212bj106ml 10 0805 table 3. capacitors for c in and c out recommended component selection for typical application figure 4. pcb layout guide shdn/rt gnd pgnd lx comp fb pgood pvdd vdd lx 9 8 7 1 2 3 4 5 10 6 gnd 11 r osc r comp c comp gnd r2 v out r1 c f gnd c1 r3 c in v in gnd c out v out l1 place the input and output capacitors as close to the ic as possible lx should be connected to inductor by wide and short trace, keep sensitive components away from this trace. place the feedback and compensation components as close to the ic as possible
RT8055B 13 ds8055b-03 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 2.950 3.050 0.116 0.120 d2 2.300 2.650 0.091 0.104 e 2.950 3.050 0.116 0.120 e2 1.500 1.750 0.059 0.069 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 10l dfn 3x3 package 1 1 2 2 note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options d 1 e a3 a a1 d2 e2 l b e see detail a

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